1. Field of the Invention
This invention relates to a driving circuit for a charge transfer apparatus. More particularly, it relates to a driving circuit in which its high frequency characteristics and the precise delay time can be kept even in the case where the charge transfer apparatus having a multi-stage charge coupled device is driven with high frequency.
2. Description of the Prior Art
FIG. 1 shows a prior art driving circuit for a charge transfer apparatus. As shown in the figure, the driving circuit is comprised of a charge coupled device (CCD) 2, an output signal processing circuit 3, a signal output terminal 4, a clock buffer 5, a clock logic 6, and a clock input terminal 8. In this circuit, said CCD 2, signal processing circuit 3, and signal output terminal 4 compose the charge transfer apparatus.
In the prior art driving circuit shown in FIG. 1, a basic clock (for example, 4 fsc=14.3 MHz ) is input through clock input terminal 8 in order to drive CCD 2. The input clock is then shaped in its wave form by clock logic 6 to generate required timings. This clock is then input to clock buffer 5 in order to drive CCD 2. This CCD 2 has a signal input means and a signal output means, each of which converts electric signals to charge signals and vice versa. Thus, once electric signals are input to CCD 2 through the signal input means, these are converted to charge signals there and transferred to the signal output means where the charge signals are converted to electric signals again. The output signals from CCD 2 are then processed through signal processing circuit 3 and output through output terminal 4.
In usual, a CCD having about 910 stages is required to delay 1H (one horizontal scanning period=63.5 .mu.sec) in the NTSC system with clock frequency 4 fsc=14.3 MHz. On the other hand, about 2270 stages are required to realize a 2H delay in the PAL system with clock frequency 4 fsc=17.7 MHz. For a still longer delay line to realize a broad-band transmission, the required stages of a CCD increase enormously.
Under such a condition, it is necessary to increase the load capacity of clock buffer 5 and, as well, to enlarge the size of clock logic 6. Accordingly, even though the buffer size (for example, channel width for MOS buffers) is enlarged in order to obtain desired frequency characteristics, the buffer becomes saturated in its speed. So, excellent characteristics cannot be obtained from the prior art driving circuit.
As mentioned above, when the prior art driving circuit drives a multi-stage charge transfer apparatus with high frequency so as to keep excellent frequency characteristics, the following disadvantage arises. That is, in that case, the load capacity of the driving circuit for the charge transfer apparatus increases so much that the driving circuit becomes saturated in its speed. As well, the driving ability becomes saturated. As a result, excellent frequency characteristics cannot be realized in the prior art driving circuit.